As semiconductor devices become more dense, there is a desire to make device junction regions such as complimentary metal-oxide semiconductor (CMOS) source/drain regions shallower. In addition, advanced semiconductor technologies (such as CMOS and BiCMOS) require low-resistance contacts to high quality device junctions to improve device performance. As the junction regions become shallower, it becomes harder to make contact to the junction regions without significantly increasing the junction electrical leakage current. It is desired to keep the p.sup.+ n and n.sup.+ p junction leakage current minimal in order to reduce the overall chip power consumption and improve the device manufacturing yield. The device junction leakage is influenced by numerous factors including substrate damage and overetch during the contact etch process.
The device contact etch processes are usually anisotropic based on reactive ion etching (RIE) and can generate damage to the substrate and silicon overetch in the contact region. During the etch, various species (hydrogen, carbon, etc.) get implanted into the junction regions near the contact surface. Increased junction leakage occurs when electrically active defects exist close to the p.sup.+ n or n.sup.+ p junction space charge region. Moreover, the contact etch processes usually employ as much as a 50-100% overetch to ensure cleared contact holes over the entire wafer surface. Although the contact oxide etch is typically selective against silicon, some loss of silicon underneath the contact holes occurs during the overetch period. The combination of silicon loss due to overetch and the RIE-induced substrate damage can cause serious junction leakage problems. The increased junction leakage is due to the electrically active defects within the junction space charge or depletion region. Moreover, the subsequent contact silicidation process used to obtain low contact resistance can increase the possibility of junction leakage problem due to the silicon consumption by the contact silicide. In order to avoid the contact related junction leakage problems, the heavily doped source/drain junctions must be made deep enough such that all the substrate defects generated by the contact etch damage and substrate overetch remain above and outside the junction depletion region. This requirement, however, can result in increased punch-through leakage (unwanted leakage through the channel from source to drain) in MOSFETs which, in turn, limits the scalability of the device. Accordingly, there is a need for a method to form low leakage device junction without sacrificing device scalability and without degrading device performance.